Confused decoupling technics for TM4C in System Design Guidelines for Tiva C family

https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/503320/1827267

It's about  System Design Guidelines for the TM4C129x Family

Confusing moment at page 20, Figure 18

Authors say what best practice is A (capacitor places outside trace )

But in other literature and guides best practice is such placement when capacitor places between via to power plane and MCU pin and trace is short is possible. Example:

As I know it's a common practice.

There are the reasons for such placement (as on Picture A) in case of Tiva C?

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Danil Borchevkin
Kaliningrad, Russia
www.lab409.ru

 spma056, Decoupling, system level design, PCB, Tiva C, TM4C, power decoupling